Ph.D. student specializing in Machine Learning and Computer Engineering.

I’m a member of the Adaptive Computing and Embedded Systems Lab in the Electrical and Computer Engineering Department at UC San Diego, advised by Professor Farinaz Koushanfar.

My research interests include machine learning, speech and natural language processing, statistical modeling, reinforcement learning, adversarial learning, systems security and vulnerability analysis of deep learning models.

I received my B.Sc. in Electrical Engineering from University of Massachusetts, Amherst and B.A in Physics from Mount Holyoke College in 2015 and 2014, respectively. Prior to pursuing my research interests in academia, I worked as an Applications Engineer at Global Foundries New York. I’m a recipient of Charles Lee Powell Foundation Fellowship.


  • Our paper Waveguard: Understanding and Mitigating Audio Adversarial Attacks got accepted at USENIX Security 2021!

  • Our paper on Adversarial Deepfakes got accepted at WACV 2021!


  • Waveguard: Understanding and Mitigating Audio Adversarial Attacks

    Shehzeen Hussain*, Paarth Neekhara*, Shlomo Dubnov, Julian McAuley, Farinaz Koushanfar
    USENIX Security Symposium (USENIX) 2021
    [ * Equal Contribution ]
    [ paper]

  • Adversarial Deepfakes: Evaluating Vulnerability of Deepfake Detectors to Adversarial Examples

    Shehzeen Hussain*, Paarth Neekhara*, Malhar Jere, Farinaz Koushanfar, Julian McAuley
    Winter Conference on Applications in Computer Vision (WACV) 2021
    [ * Equal Contribution ]
    [ paper, video examples ]

  • Universal Adversarial Perturbations for Speech Recognition Systems

    Paarth Neekhara*, Shehzeen Hussain*, Prakhar Pandey, Shlomo Dubnov, Julian McAuley, Farinaz Koushanfar
    Interspeech 2019
    [ * Equal Contribution ]
    [ paper, audio examples ]

  • Adversarial Reprogramming of Text Classification Neural Networks

    Paarth Neekhara, Shehzeen Hussain, Shlomo Dubnov, Farinaz Koshanfar
    Conference on Empirical Methods in Natural Language Processing and 9th International Joint Conference on Natural Language Processing 2019 (EMNLP)
    [ paper, code ]

  • FastWave: Accelerating Autoregressive Convolutional Neural Networks on FPGA

    Shehzeen Hussain, Mojan Javaheripi, Paarth Neekhara, Ryan Kastner, Farinaz Koushanfar
    International Conference On Computer Aided Design 2019 (ICCAD)
    [ paper]

  • Overlay optimization for 1x node technology and beyond via rule based sparse sampling

    Nyan Lynn Aung, Woong Jae Chung, Lokesh Subramany, Shehzeen Hussain, Pavan Samudrala, Haiyong Gao, Xueli Hao, Yen-Jen Chen, Juan-Manuel Gomez
    Metrology, Inspection, and Process Control for Microlithography 2016 SPIE
    [ paper ]

Relevant Experience

  • Facebook AI Research

    June 2020 - September 2020
    Menlo Park, California

    Research Intern
    I was a member of the Text-to-Speech Synthesis team within Applied AI Speech. I developed deep neural network models for multi-speaker and multi-style controllable speech synthesis. I also designed end-to-end pipeline for joint training of speaker encoder model with text-to-speech synthesis (Tacotron2) model. Additionally, I developed a voice cloning toolkit for synthesizing speech of unseen speakers from a few reference audio samples.

  • Intel Corporation

    July 2019 - October 2019
    Santa Clara, California

    Graduate Machine Learning Intern
    I was a part of the Non-Volatile Memory Systems Group, working on reinforcement learning for memory and SSD applications.

  • Qualcomm Technologies Research

    June 2018 - September 2018
    San Diego, California

    Deep Learning R&D Intern
    I was a part of Qualcomm Research optimizing power and performance management on Qualcomm chipsets using reinforcement learning with deep neural networks. I was advised by Shankar Sadasivam, Manu Rastogi, Guillaume Sautière and Rajeev Jain.

  • GlobalFoundries

    July 2015 - August 2017
    Malta, New York

    Process Engineer
    Among other responsibilities, I was a member of the applications team and assisted in design of algorithms to model advanced wafer level corrections.
    [ paper ]